As the size of integrated circuits decreases, it has become desirable to increase the density of the arrangement of FET devices on a substrate. Vertical fin-based field-effect transistor (finFET) devices have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area overlying a substrate. However, as circuits are scaled to smaller dimensions and thus a smaller area, the lateral spacing between adjacent vertical fins may become too small to enable the vertical finFET devices to operate properly. Stacked nanosheet FETs have been developed to further enable larger effective conduction width in a small layout area overlying a substrate. A stacked nanosheet FET may include multiple nanosheets arranged in a three dimensional array on a substrate with a gate stack formed on a channel region of ones of the nanosheets. The gate stack may surround four sides of the channel region of a nanosheet (gate-all-around).